1. Field of the Invention
The present invention relates to a data error correction system which is used for improving the link quality of a transmission link by coding data into error correction codes so as to correct errors generated in the transmission link in so far as possible, in the fields of satellite communication and space communication which transmit data such as compressed image data.
2. Background Art
There is a data error correction method in digital communication called the xe2x80x9cViterbi decoding methodxe2x80x9d (G. D. Forney Jr., xe2x80x9cThe Viterbi Algorithmxe2x80x9d, 3 Proceedings of IEEE, vol. 61, pp. 268-278, March 1973). Improved error correction for encoded data by a combination of a convolutional code with another code is proposed by G. D. Forney Jr. Another code generally used is a concatenation of a convolutional code and a Reed-Solomon code which is obtained by combining a block convolutional coder and a Reed-Solomon coder. The decoding of the encoded data is carried out based on the Viterbi algorithm and the Viterbi decoded data is subjected to Reed-Solomon decoding.
However, since the error correction is executed independently by the Viterbi decoder and by the Reed-Solomon decoder, the above-described conventional data error correction system has a problem in that the conventional error correction system is not capable of sufficient error correction effect to improve the line quality of some transmission links.
It is therefore an object of the present invention to solve the above described problem, and to provide an error correction system which is capable of correcting data errors iteratively, sufficiently correcting bit errors generated in the transmission link, and improving the link quality.
According to the first aspect of the present invention, a data error correction system comprises: a buffer for receiving data which are encoded by a block encoder and a convolutional encoder; a Viterbi decoder for decoding a block of data designated from the data output from said buffer in accordance with the Viterbi algorithm; a block decoder, which starts decoding when it receives data corresponding to a block code length from said Viterbi decoder, for executing the error correction when possible and outputting the result and a control circuit which controls the re-decoding by said Viterbi decoder so as to make it possible to execute decoding by said Viterbi decoder for data corresponding to the block code length whose error could not be corrected yet, based on an error detection signal output by said block decoder, when the error correction has not been completed.
According to the second aspect of the present invention, the data error correction system according to the first aspect is provided, wherein the data error correction system allows repeated executions of decoding by the Viterbi decoder and the block decoder responsive to the error detection signal until the error correction is completed.
According to the third aspect of the present invention, the data error correction system according to the first aspect is provided, wherein data input into said buffer is the bit data expressed by soft decision representation.
According to the fourth aspect of the present invention, the data error correction system according to the first aspect is provided, wherein said Viterbi decoder comprises: a branch-metric generator for obtaining a probability of each transmittable symbol having been transmitted, when the data for respective symbols output from said buffer are received; a path-metric register which stores the cumulative metrics of the survival paths; an addition comparison selection circuit for outputting a path-metric value at the n-th state and a selection information at the n-th state selected by executing comparison, addition, and selection of outputs of said path-metric register and said branch-metric register at every symbol time along the trellis a maximum likelihood path state number order detector for obtaining a state number which has the maximum path-metric value among path-metric values at the n-th state output from said addition comparison selection circuit; a path memory for storing at every symbol time the selection information at the n-th state output from said addition comparison selection circuit; a trace back circuit for outputting a decoded data with (u+k) bits from the last bit that arrived when tracing back to the past from the state number output of the maximum likelihood state number order detector at every (u+k)-th time, when the encoded data are divided into data having a length of k bits and the data with u bit length is added to the divided data having k bit length as the redundancy data; and a decoding control circuit for allowing execution of re-decoding when receiving a control signal from said control circuit.